Three-Dimensional Electrostatic Effects of CNTs -my research work

SINGLE wall carbon nanotubes (CNTs) are of great interest for future electron device applications because of their excellent electrical properties. Electrostatics are an important factor in transistor performance and therefore need to be carefully studied. It is well known that the electrostatics of CNT devices can be significantly different from bulk devices due to the one-dimensional (1-D) channel geometry. Previous theoretical studies of CNT-FET electrostatics assumed a coaxial geometry . These studies thoroughly described the role of the two–dimensional (2-D) coaxial environment on the electrostatics of the 1-D channel. The coaxial geometry provides good gate control with subthreshold swings very close to 60 mV/decade, and the oxide thickness and dielectric constant both play an important role by determining the gate capacitance of the device. The contact geometry also plays an important role in the transfer of charge from the metal contact to the CNT. For low Schottky barriers (SB), a large charge transfer can be achieved if the contact has a large surface area and the oxide dielectric constant is large. Thin oxides and small contact areas can achieve very short electrostatic scaling lengths (the distance by which the source and drain fields penetrate into the channel) and therefore good electrostatic behavior. While a coaxial geometry provides important qualitative insights into the behavior of experimental devices (which typically have a planar top or bottom gated geometry), a full threedimensional (3-D) treatment of planar devices is needed. In this paper, we performed a careful study of the 3-D electrostatics of planar-gated CNTFETs. Our objective is to provide both qualitative and quantitative insights valid for realistic devices. Several of the results are analogous to those that occur in a coaxial geometry, but we show quantitatively how they play out in a realistic planar geometry. The results should be useful for interpreting experiments and for designing high-performance CNTFETs. Among the several techniques available to treat 3-D electrostatics, we find the method of moments (also known as the boundary element method) well suited for simulating planargate CNTFETs. This method is computationally inexpensive because it uses grid points only on the surfaces where charge exists and not in the entire 3-D domain. The computational domain is thus reduced only to the important device regions: the channel, the contacts, and the gate. The problem of boundary conditions in the open areas and termination of the simulation domain does not appear at all. Since all the boundary elements are assumed to be point charges, the electrostatic potential of the system decays to zero at infinity, where both the potential and electric field are zero. In this way, the method of moments inherently assumes a zero-field boundary condition as the distance , whichfacilitates the simulation of devices with electrostatically open boundaries, (e.g., the back-gated CNTFET).

We examine the effect of the oxide thickness, the oxide dielectric constant, and the contact geometry for two different device geometries, the bottom-gated (BG) and top-gated (TG) devices shown in Fig. 1.We will show that for a CNTFET with either of these two geometries, the scaling length is mostly determined by the gate oxide thickness. The geometry of the source and drain contacts can also play an important role. The BG device is more sensitive to the contact width rather than the contact height because a wider device more effectively screens the gate field and prevents it from terminating on the CNT.We will also show that high-k dielectric materials do not offer a significant advantage for the BG device because the oxide thickness plays the dominant role. Both the effects of contact height and high-k materials are, however, more pronounced for the TG device, where the high-k dielectric in the upper region increases not only the gate to CNT coupling, but also the contact-to-CNT coupling and the contact-to-gate parasitics as well. When the contacts are thick and can screen the gate field and prevent it from terminating on the channel, high-k dielectrics can actually degrade the electrostatic performance of the device. A careful geometry optimization for the contacts of planar short channel devices is, therefore, important. A properly designed TG device with very thin gate oxide can provide near ideal subthreshold behavior, similarly to what is predicted for coaxial geometries. Finally, we find that one-dimensional “needle-like” contacts offer the best electrostatic performance. In practice, however, this advantage would have to be balanced against the increased series resistance.